1. Field of the Invention
The present invention relates to a system controlled by a direct memory access (hereinafter referred to as DMA) method.
A DMA control unit is used in a computer system to reduce the load on a central processing unit (CPU) by transferring data between a main memory and submemory and transferring data between a submemory and an auxiliary memory. The "main memory" refers to the system memory which performs data communication with the CPU and is also called the main storage. The "submemory" is the memory which performs data communication with the main memory and, for example, corresponds to a so-called disk cache memory. Further, the "auxiliary memory" is an external memory which, for example, corresponds to a disk memory. Usually, a plurality of disk memories are provided. Disk memories, i.e., auxiliary memories, are connected to the DMA control unit through auxiliary memory control units, i.e., disk control units, provided corresponding to the same. Similarly, the disk cache memory is connected to the DMA control unit through a memory-to-memory transfer control unit. In this case, the total of the sum (CP.sub.dk) of the data transfer capacities of the respective disk control units and the data transfer capacity (CP.sub.mm) of the memory-to-memory transfer control unit (CP+CP.sub.mm) must be smaller than the data transfer capacity (CP.sub.dma) of the DMA control unit, i.e., CP.sub.dk +CP.sub.mm .ltoreq.CP.sub.dma. If the inequality symbol (&lt;) becomes opposite, the DMA control unit would become inoperative due to insufficient capacity. In this case, it would be possible to increase the data transfer capacity of the DMA control unit to make up for the insufficient capacity but this would require an increase in the amount of hardware in the DMA control unit and would not be advantageous from an economic viewpoint.
2. Description of the Related Art
As described later in detail in conventional DMA control units, a status of the subchannel (control information for each of the above DMA control units) is not known. Therefore, even when the number of data transfer requests becomes a maximum, a certain restriction is applied so that the data transfer capability (CP.sub.dma) of the DMA control unit is not exceeded. This restriction means that the data transfer capacity of the memory-to-memory transfer control unit is always kept at a constant level (for example, 1 Mbyte).
Therefore, when one of two disk control units does not issue a data transfer request to the DMA control unit, that is, when there is a margin in the capacity of the DMA control unit, despite it being possible to increase the data transfer capacity of the memory-to-memory control unit by an amount corresponding to the margin, the data transfer capacity of the memory-to-memory transfer control unit remains restricted to the set level (for example, 1 Mbyte). Therefore, in a conventional DMA controlled system, there is the disadvantage of a deteriorated data transfer efficiency.